Projects.

5-stage Pipelined RISC-V Processor

Complete

A SystemVerilog RV32IM core with forwarding, load-use hazard detection, and an iterative multiply/divide unit. Implemented on a PYNQ-Z2 FPGA and verified using self-checking benchmarks.

  • SystemVerilog
  • Vivado
  • Yosys
  • OpenSTA
92.7 MHzFPGA implementation
0.67–0.75IPC on tested benchmarks
View repository
Design and measurement details

Five in-order stages, EX-stage branch resolution, and a 37-cycle iterative multiply/divide unit. Benchmarks include CRC-32, Towers of Hanoi, bubble sort, FIR filtering, and matrix multiplication. SkyWater 130 nm synthesis estimates: 94 MHz, 0.088 mm², and 8.7 mW before physical layout. SoC integration is in progress.

Asynchronous FIFO

Complete

A dual-clock FIFO that moves data between independent clock domains using Gray-coded pointers and synchronizers. Verified with UVM, including checks for full and empty detection, reset behavior, and data ordering.

  • SystemVerilog
  • UVM
  • Clock domain crossings
View repository

Single-Cycle RISC-V Processor Tapeout

Complete

An ASICWRU Tiny Tapeout project built around a single-cycle RISC-V processor. The CPU runs a simple counter program and drives a seven-segment display.

  • Verilog
  • RISC-V Assembly
  • LibreLane
View repository
Image from u/Dannypan